Logic circuitry adapted to control the transfer of information to a storage elements



June 13, 1967 GLOATEs ETAL 3,325,790

LOGIC CIRCUITHY ADAPTED TO CONTROL THE TRANSFER OF INFORMATION TO ASTORAGE ELEMENT Original Filed Oct. 14, 1960 Mm v 573 f l, cola MEANS oT ,ex

Z n m -na 1 FL m-rwp [#1210 Z. Fix 002v BYZ/ i Z yaw/Ill United StatesPatent LOGIC CIRCUITRY ADAPTED TO CONTROL THE TRANSFER OF INFORMATION TOA STORAGE ELEMENT Eli Gloates, Haddonfield, N.J., and Laszlo L.Ralroczi, Phoenix, Ariz., assignors to Radio Corporation of America, acorporation of Delaware Original application Oct. 14, 1960, Ser. No.62,644, now Patent No. 3,234,518, dated Feb. 8, 1966. Divided and thisapplication July 15, 1964, Ser. No. 382,911

7 Claims. (Cl. 340-173) This application is a division of applicationSer. No. 62,644, filed Oct. 14, 1960, titled, Data Processing System,and issued as Patent No. 3,234,518 on Feb. 8, 1966.

The object of this invention is to provide an improved system fortransferring binary information through an input gate to a storagedevice.

The storage device of the present circuit may be a fiipflop having a setinput terminal and a reset input terminal. The circuit includes twologic gates, the first for information fiow and connected at its outputto the set terminal, and the second for resetting the flip-flop andconnected at its output to the reset terminal. The data transfer commandinput terminal is connected to one input of the first gate and isconnected through separate paths, one including a delay means, to bothinputs of the second gate. In response to the absence of the read-incommand, the first logic gate is maintained disabled through itsconnection to the read-in command terminal and the secand logic gate ismaintained primed through the path which includes the delay means. Inresponse to the data transfer command, the first gate becomes primed,and the other path to the second gate applies an enabling signal to thesecond gate, causing the second gate to apply a reset signal to theflip-flop. After the delay inserted by the delay means, the priminginput applied to the second gate by the path including the delay meanschanges to a disabling input, thereby removing the reset signal from theflip-flop. The delay interval, however, is of shorter duration than theread-in command so that the first input gate continues to remain primedafter the second gate is disabled. Accordingly, after the automaticreset of the flip-flop, information may flow through the first gate tothe flip-flop.

The invention is discussed in greater detail below and is illustrated inthe drawing, the single figure of which is a block circuit diagram ofthe invention.

In the circuit of the present invention, electrical signals manifestbinary digits (bits). A signal at one level represents the bit 1, and asignal at another level represents the bit 0. To simplify the followingdiscussion, the bit itself rather than the signal manifesting that bitis referred to.

The logical elements shown in the figure are in themselves known. TheAND gate produces a 1 output in response to two 1 inputs and a 0 outputin response to all other input conditions. The NONE gate, sometimes alsoknown as a NOR gate, produces a 1 output in response to two 0 inputs anda 0 output in response to all other input conditions. An inverterproduces the complement or the input bit applied thereto. The delaymeans 243 introduces a relatively short delay, shorter than the durationof the input command SRXR=1.

The circuit shown includes a flip-flop having set (S) and reset (R)input terminals. A 1 applied to the set terminal causes the flip-flop toassume one state and a 1 applied to the reset terminal causes theflip-flop to assume its other state. AND gate 60 is connected to the setterminal and NONE gate 229 is connected to the reset terminal. The datatransfer command signal SRXR is applied to the common input terminal 16.Inverter 226 is connected to input terminal 10 and applies its outputboth to NONE gate 229 and to inverter 240'. The inverter 240 isconnected through lead 245 and delay means 243 to the second input toNONE gate 229.

In the operation of the circuit above, SRXR is initially equal to 0.Thus, AND gate 60 is disabled. The inverter 226 produces an output mm.This 1, appearing on the input lead 12, disables NONE gate 229. However,the inverter 240 and delay means 243 derive from m l an output COR=0vCOR=0 is a priming signal for NONE gate 229.

When it is desired to initiate the transfer of a data bit into theregister, the transfer command SRXR is changed to 1. The 1 acts as apriming signal for AND gate 60. Inverter 226 produces an output smzo oninput lead It) to NONE gate 229. The second input is COR=O so that NONEgate 229 becomes enabled and produces a reset pulse RX: 1, which isapplied to the reset terminal of the flip-flop. However, after a shortdelay interval inserted by delay means 243, the bit on lead 245, whichis equal to 1, appears as COR=1 on the second input lead to NONE gate229. This signal disables the NONE gate, removing the reset signal fromthe flip-flop.

The duration of the signal SRXR=1 is greater than the delay inserted bythe delay means 243. Accordingly, AND gate 60 remains primed after theNONE gate 229 has become disabled and after the reset signal RX=1 isremoved from the flip-flop. Therefore, any data bit present at the datainput terminal 14 passes through AND gate 60 to the flip-flop. If thedata bit is a l, the flip-flop becomes set, indicating storage of a 1;if the data bit is a 0, the flipllop remains reset, indicating storageof a O.

The circuit discussed above appears in the parent application in threedifferent figures. The AND gate 60 and the flip-flop appear in FIGURE 2.Inverter 226 and NONE gate 229 appear in FIGURE 13. Inverter 240 anddelay means 243 appear in FIGURE 14. To permit the reader more easily tosee where in the system of the parent application the present circuitsare found, the reference numerals and letters of the parent applicationare applied to the corresponding circuit elements and leads of thepresent figure. In addition, the numerals 10, 12 and 14 have been addedto the present figure to help the reader follow the explanation.

What is claimed is:

1. In combination,

a two-state circuit having a set input terminal and a reset inputterminal;

two logic gates, the first connected at its output to the set terminal,and the second connected at its output to the reset terminal; and

means responsive to a single selection signal for concurrentlyenergizing the second gate causing it to apply a reset signal to thetwo-state circuit, and priming the first gate, and, after apredetermined interval, disabling the second gate.

2. In combination,

a two-state circuit having a set input terminal and a reset inputterminal;

two logic gates, the first connected at its output to the set terminal,and the second connected at its output to the reset terminal; and

means for concurrently applying a reset signal to the two-state circuitand priming the first gate, said means including:

a common terminal; means including delay means connected between saidcommon terminal and the second gate for priming the second gate inresponse to the manifestation at said common terminal of a bit of onevalue and disabling the second gate in respouse to the manifestation ofsaid common terminal of a bit of opposite value; and

means responsive to a change at said common terminal from themanifestation of a bit of said one value to the manifestation of a bitof said opposite value for concurrently priming the first gate, andapplying an enabling signal to the second gate causing the second gateto apply a reset signal to the two-state circuit, whereby, after thedelay interval inserted by the delay means, the second gate becomesenabled.

3. In combination,

a two-state circuit having a set input terminal and a reset inputterminal;

two logic gates, the first connected at its output to the set terminal,and the second connected at its output to the reset terminal; and

means for concurrently applying reset signal to the two-state circuitand priming the first gate, said means including:

a common terminal;

means including delay means connected between said common terminal andthe second gate for priming the second gate in response to the presenceof a signal representing the bit zero at said common terminal, anddisabling the second gate in response to the presence of a signalrepresenting the bit one at said common terminal; and

means responsive to a change in the signal at said common terminal fromone representing the bit zero to one representing the bit one forpriming the first gate and applying an enabling signal to the secondgate causing the second gate to apply a reset signal to the two-statecircuit, whereby, after the delay interval inserted by the delay means,the second gate becomes disabled.

4. In combination,

a flip-flop having set and reset input terminals;

a two-input first logic gate connected at its output terminal to saidset terminal;

a two-input second logic gate connected at its output terminal to saidreset terminal;

a priming signal input terminal connected to both gates which, whenactive, places each gate in condition to conduct;

means for inverting and delaying a signal coupled between said primingsignal input terminal and the second input terminal to said second gate,said means serving to disable the second gate after the delay itinserts, in response to a priming signal; and

a data signal input terminal connected to the second terminal of saidfirst gate.

5. In combination,

a flip-flop having set and reset input terminals;

a two-input AND gate connected at its output terminal to said setterminal;

a two-input NONE gate connected at its output terminal to said resetterminal;

a priming signal input terminal directly connected to the AND gate andconnected through an inverter to the NONE gate;

means for inverting and delaying a signal coupled between the output ofsaid inverter and the second input to said NONE gate; and

a data signal input terminal connected to the second terminal of saidAND gate.

6. In combination,

a two-state circuit having a set input terminal and a reset inputterminal;

two logic gates, the first connected at its output to the set terminaland the second connected at its output to the reset terminal;

read-in command input terminal means connected to. both gates forapplying a disabling signal to a first terminal of each gate and apriming signal to the second terminal of the second gate in the absenceof a read-in command signal, and for applying a priming signal to saidfirst terminal of each gate and a disabling signal to said secondterminal of the second gate in response to the presence of a read-incommand signal; and 1 a delay means in the path between the selectioninput terminal and the second terminal of the second gate.

7. In the combination set forth in claim 6, said first gate being an ANDgate and said second gate being 11 NONE gate.

No references cited.

BERNARD KONICK, Primary Examiner.

J. BREIMAYER, Assistant Examiner.

4. IN COMBINATION, A FLIP-FLOP HAVING SET AND RESET INPUT TERMINALS; ATWO-INPUT FIRST LOGIC GATE CONNECTED AT ITS OUTPUT TERMINAL TO SAID SETTERMINAL; A TWO-INPUT SECOND LOGIC GATE CONNECTED AT ITS OUTPUT TERMINALTO SAID RESET TERMINAL; A PRIMING SIGNAL INPUT TERMINAL CONNECTED TOBOTH GATES WHICH, WHEN ACTIVE, PLACES EACH GATE IN CONDITION TO CONDUCT;MEANS FOR INVERTING AND DELAYING A SIGNAL COUPLED BETWEEN SAID PRIMINGSIGNAL INPUT TERMINAL AND THE SECOND INPUT TERMINAL TO SAID SECOND GATE,SAID MEANS SERVING TO DISABLE THE SECOND GATE AFTER THE DELAY ITINSERTS, IN RESPONSE TO A PRIMING SIGNAL; AND A DATA SIGNAL INPUTTERMINAL CONNECTED TO THE SECOND TERMINAL OF SAID FIRST GATE.